Shift Register problem

[heywoodp]

I'm building a cockpit using PMDG. Got all the MCP inputs done using 3 74hc165's and the SPI interface onto an Arduino mega. I've now started to look at the two EFIS panels both with some 32 inputs each. My idea was to have a sub-board for each using with its own register bank. I was hoping to use the same SPI interface for all three and use the chip enable line of the 74hc165's to select which bank I was going to bring in. Didn't work. Back to the head scratching, so I tried 'anding' the clock signal with an 'bank select' output from the Arduino hoping I could then switch the serial clock 'on' to the various banks.. This appeared to work for the selected bank but I also got an input from one of the other banks but only 'bit 7'Back to the breadboard. I've got 2 165's in series. All the inputs on the MSB 165 are grounded. If I gate the 'serial clock' through to the registers then all is fine. However is I inhibit the clock then all the inputs stop as expected apart from bit 7. This results in FF being presented on the MOSI line into the arduino. All the inputs are held low via a 10k to ground. I've tried the other keys and all from 0 to 6 function as expected in that when the clock is absent there is now input. If key 7 is pressed I get FF sent to the MOSI. Any clues. I could provide a diagram if needed

[RadarBob]

Sounds interesting - I have played a bit with the 74165.

Must admit I'm finding it a bit difficult to visualise what you are doing without a drawing though.

Any chance you could put one up?

Cheers,

Rob

[RadarBob]

Just a couple of thoughts:

Have you any buffering between the output of each bank of registers and the SPI input line?

If not, you might think about putting in a tri-state device like 74hc125 and controlling each gate with a chip select line.

Also, you might check the 74165 datasheet advice regarding the relative states/timings for the use of the Shift/NOT Load line and the clock inhibit.

Particularly:

Clocking is accomplished through a two-input
positive-NOR gate, permitting one input to be
used as a clock-inhibit function. Holding either of
the clock inputs high inhibits clocking, and holding
either clock input low with SH/LD high enables the
other clock input. Clock inhibit (CLK INH) should
be changed to the high level only while CLK is
high. Parallel loading is inhibited as long as SH/LD
is high. Data at the parallel inputs are loaded
directly into the register while SH/LD is low,
independently of the levels of CLK, CLK INH, or
serial (SER) inputs.

Cheers,

Rob

[heywoodp]

Hi Rob, thanks for your input. I've attached a rough circuit diagram. I've disconnected IC2 so there is only IC1 in the circuit and put DS on pin 10 down to gnd. The switch inputs are on D0, D1,D6 and D7. The other inputs are to gnd. When the clock is direct onto pin 2, it appears to function ok. If the clock is high, I get no output as expected unless I switch D7

As I said in my original explanation, my pan was to have a separate daughter board for the MCP and 2 EFIS panels and use a 'board select' signal to select the required board. As you suggest, I'll check the datasheet.

[RadarBob]

Thanks for the drawing - All understood - You haven't got as far as connecting multiple banks yet - So no worries about about contention.

As far as I understand it, changing the state of the inputs should have no effect whilst NOT PL is high.

Normally, NOT PL would be toggled from high-low-high to latch in (capture) the switch states at one moment in time, and then those switch states are clocked out.

- So if you are holding Not PL high and the clock pulses are inhibited and bits are still being clocked out, then something weird is happening.


Actually, I am not sure why you could not get the on-board clock gating to work - It should do what you want.

Cheers,

Rob

[RadarBob]

Looking at the 74165 datasheet it appears that the output will change to reflect the state of D7 when a PL toggle is performed (regardless of the state of CLK/CLK INH/DIN - So if PL is common to all banks and you toggle it in order to load one of your other banks.....

If that is the case, the only way round that I see is to perform the selection on the output side - You are going to have to do that anyway I think.

[heywoodp]

Hi Rob, thanks for your input. Guess its back to the breadboard tomorrow and try a few of these ideas out. Your last comment about D7 and PL sounds something like what is happening. Time to re-read the datasheet.

paul.h

[RadarBob]

Hi Paul,

You are welcome hope it helps - Good luck with the testing and hope you sort it out.

You might want to think about gating both the clock and the output.

I haven't fully thought it through, but I think you would get away with just selecting the output if you have the same number of registers in each bank.

But if you can get the on board clock gating to work you can do away with your external clock gates.

I would then look at using that tri-state buffer 74HC125 or similar. You get four gates in a package so I think that will cover your requirement.

Looks like the enable for the buffer is low and high to put it into tri-state - So you could connect your bank select to the register clock enables and the buffer and it should work I think.

If you haven't seen it already, you might take a look at the Texas 74LS165 datasheet - Not the same beast I know - But the functionality is the same and I think it is clearer than some I have seen.

Would be interested to hear how you get on.

Cheers,

Rob

[RadarBob]

Or you could look at 74hc589 - Its a parallel load shift register with a tri-state output.

[xplanematt]

Or, there's this:

http://macetech.com/store/index.php?main_page=product_info&products_id=23

I love coding, Arduinos, and figuring out new circuits, but simple switch I/O is one of those mundane but requisite tasks that I don't really feel the need to reinvent every time I add some more inputs.

It's your call, but my advice is use COTS building-blocks for the basic stuff, and save your brain power for the task of tying it all together. Let the Centipede and its ready-to-rock software library monitor your inputs, put your time into cool stuff like software-based PWM to run odd DC motors, methods for reading tach generators, creating multiphase AC signals, etc...................

Matt

[heywoodp]

Looking at the 74165 datasheet it appears that the output will change to reflect the state of D7 when a PL toggle is performed (regardless of the state of CLK/CLK INH/DIN - So if PL is common to all banks and you toggle it in order to load one of your other banks.....

If that is the case, the only way round that I see is to perform the selection on the output side - You are going to have to do that anyway I think.

Hi Rob, managed to get it going at long last. Your bit above proved to be the root cause of the problem. I now NAND the output with a 'bank select' signal, do the same to the EFIS banks, then bring all three together in a 4 input Nand gate which not only brings them all together but also inverts the input to correct the previous inversion.

Thank once again for your help

[RadarBob]

Hi Paul,

Great news! - Glad you found a solution and thanks for the update.

Are you finding that you can read the inputs in fast enough?

I think your processor is quite quick, so I shouldn't have thought that you would have an issue there.

Cheers,

Rob