Shift Register problem

[heywoodp]

Looking at the 74165 datasheet it appears that the output will change to reflect the state of D7 when a PL toggle is performed (regardless of the state of CLK/CLK INH/DIN - So if PL is common to all banks and you toggle it in order to load one of your other banks.....

If that is the case, the only way round that I see is to perform the selection on the output side - You are going to have to do that anyway I think.

Hi Rob, managed to get it going at long last. Your bit above proved to be the root cause of the problem. I now NAND the output with a 'bank select' signal, do the same to the EFIS banks, then bring all three together in a 4 input Nand gate which not only brings them all together but also inverts the input to correct the previous inversion.

Thank once again for your help

[RadarBob]

Hi Paul,

Great news! - Glad you found a solution and thanks for the update.

Are you finding that you can read the inputs in fast enough?

I think your processor is quite quick, so I shouldn't have thought that you would have an issue there.

Cheers,

Rob